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W986432AH 512K x 4 BANKS x 32 BITS SDRAM
GENERAL DESCRIPTION
W986432AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words x 4 banks x 32 bits. Using pipelined architecture and 0.20 m process technology, W986432AH delivers a data bandwidth of up to 732M bytes per second (-55). For different application, W986432AH is sorted into four speed grades: -55, -6, -7 and -8. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986432AH is ideal for main memory in high performance applications.
FEATURES
* * * * * * *
3.3V 0.3V power supply 524288 words x 4 banks x 32 bits organization Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8, and full page Sequential and Interleave burst Burst read, single write operation
* * * * * *
Byte data controlled by DQM Power-down Mode Auto-precharge and controlled precharge 4K refresh cycles/64 mS Interface: LVTTL Packaged in 86-pin TSOP II, 400 mil - 0.50
PIN CONFIGURATION
DQM1 DQM3 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 45 42 DQ23 VCC Q VCC Q VCC Q VCC Q VSSQ VSSQ VSSQ VSSQ
DQ9
DQ8
CKE
CLK
VSS
VSS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
VSSQ
A10/AP
DQM0
DQM2
VCC
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
VCC
VCC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CAS
RAS
VCC Q
VSS Q
VCC Q
VSS Q
VSS Q
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Publication Release Date: December 1999 Revision A1
VCC Q
VCC Q
VCC
BS0
BS1
NC
CS
NC
WE
NC
A0
A1
A2
43
2
3
4
5
6
7
8
1
9
44
VSS
Vss
NC
NC
NC
NC
A9
A8
A7
A6
A5
A4
A3
W986432AH
PIN DESCRIPTION
PIN NAME A0-A10 FUNCTION Address DESCRIPTION Multiplexed pins for row and column address. Row address: A0-A10. Column address: A0-A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. BS0, BS1 DQ0-DQ31
CS
Bank Select Data Input/ Output Chip Select
Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock RAS , CAS and WE define the operation to be executed. Referred to RAS Referred to RAS
RAS
Row Address Strobe Column Address Strobe Write Enable
CAS WE
DQM0- DQM3 CLK CKE
Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. Clock Inputs Clock Enable System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM.
VCC VSS VCCQ VSSQ NC
Power (+3.3V) Ground
Power (+3.3V) for Separated power from VCC, to improve DQ noise immunity. I/O buffer Ground for I/O buffer No Connection Separated ground from VSS, to improve DQ noise immunity. No connection
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W986432AH
BLOCK DIAGRAM
CLK CLOCK BUFFER
CKE
CONTROL
CS
SIGNAL
RAS CAS
GENERATOR
COMMAND
DECODER WE ROW DECODER COLUMN DECODER COLUMN DECODER ROW DECODER
A10
CELL ARRAY BANK #0
CELL ARRAY BANK #1
A0 ADDRESS BUFFER
MODE REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
A9 BS0 BS1
DATA CONTROL CIRCUIT
DQ BUFFER
DQ0 DQ31
REFRESH COUNTER
COLUMN COUNTER
DQM0~3
COLUMN DECODER ROW DECODER ROW DECODER
COLUMN DECODER
CELL ARRAY BANK #2
CELL ARRAY BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 2048 * 256 * 32
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Publication Release Date: December 1999 Revision A1
W986432AH
FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC +0.3V on any of the input pins or VCC supplies. After power up, an initial pause of 200 S is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as TRAS (max.).
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.
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W986432AH
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode.
Burst Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS
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Publication Release Date: December 1999 Revision A1
W986432AH
Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored.
Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 ACCESS ADDRESS n n+1 n+2 n+3 n+4 n+5 n+6 n+7 BL = 8 (disturb addresses are A0, A1 and A2) No address carry from A2 to A3 BURST LENGTH BL = 2 (disturb address is A0) No address carry from A0 to A1 BL = 4 (disturb addresses are A0 and A1) No address carry from A1 to A2
Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 ACCESS ADDRESS A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 8 BL = 4 BUST LENGTH BL = 2
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W986432AH
Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency. A Read or Write Command with auto-precharge cannot be interrupted before the entire burst operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst write cycle. This delay is referred to as write tDPL. The bank undergoing auto-precharge cannot be reactivated until tDPL and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Autoprecharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS (min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP).
Self Refresh Command
The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC cycle time plus the Self Refresh exit time. If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device.
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Publication Release Date: December 1999 Revision A1
W986432AH
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCES (min.) + tCK (min.).
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.
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W986432AH
TABLE OF OPERATING MODES
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. TABLE 1 TRUTH TABLE (NOTE (1), (2))
Command Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set No-Operation Burst Stop Device Deselect Auto-Refresh Self-Refresh Entry Self Refresh Exit Device state Idle Any Any Active (3) Active (3) Active (3) Active (3) Idle Any Active (4) Any Idle Idle idle (S.R) Clock suspend Mode Entry Power Down Mode Entry Active Idle Active (5) Clock Suspend Mode Exit Power Down Mode Exit Active Any (power down) Data write/Output Enable Data Write/Output Disable Notes: (1) v = valid, x = Don't care, L = Low Level, H = High Level (2) CKEn signal is input leve l when commands are provided. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. Active Active CKEn-1 H H H H H H H H H H H H H L L H H H L L L H H CKEn x x x x x x x x x x x H L H H L L L H H H x x DQM x x x x x x x x x x x x x x x x x x x x x L H BS0, 1 v v x v v v v v x x x x x x x x x x x x x x x A10 v L H L H L H v x x x x x x x x x x x x x x x A0-A9 V x x v v v v v x x x x x x x x x x x x x x x CS L L L L L L L L L L H L L H L x H L x H L x x RAS L L L H H H H L H H x L L x H x x H x x H x x CAS H H H L L L L L H H x L L x H x x H x x H x x
WE
H L L L L H H L H L x H H x x x X H X X H x x
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Publication Release Date: December 1999 Revision A1
W986432AH
DC CHARACTERISTICS
Absolute Maximum Rating
PARAMETER Input, Column Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current SYM. VIN, VOUT VCC, VCCQ TOPR TSTG TSOLDER PD IOUT RATING -0.3 - VCC +0.3 -0.3 - 4.6 0 - 70 -55 - 150 260 1 50 UNIT V V C C C W mA NOTES 1 1 1 1 1 1 1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to 70C)
PARAMETER Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input High Voltage Input Low Voltage
SYM. VCC VCCQ VIH VIL
MIN. 3.0 3.0 2.0 -0.3
TYP. 3.3 3.3 -
MAX. 3.6 3.6 VCC +0.3 0.8
UNIT V V V V
NOTE S 2 2 2 2
Note: VIH (max.) = VCC/VCCQ+1.2V for pulse width < 5 nS VIL (min.) = VSS/VSSQ-1.2V for pulse width < 5 nS
CAPACITANCE
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance (A0 to A11, BS0, BS1,
CS
SYM. CI
MIN. 2.5
MAX. 4
UNIT pf
,
RAS , CAS , WE ,
DQM, CKE) 2.5 CO 4 4 6.5 pf pf
Input Capacitance (CLK) Input/Output capacitance (DQ0-DQ31)
Note: These parameters are periodically sampled and not 100% tested
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W986432AH
DC CHARACTERISTICS
(VCC = 3.3V 0.3V, TA = 0~70C) PARAMETER SYM. -55 MAX. Operating Current tCK = min., tRC = min. Active precharge command cycling without burst operation Standby Current tCK = min., CS = VIH VIH/L = VIH (min.)/VIL (max.) Bank: inactive state Standby Current CLK = VIL, CS = VIH VIH/L=VIH (min.)/VIL (max.) BANK: inactive state No Operating Current tCK = min., CS = VIH (min.) BANK: active state (4 banks) Burst Operating Current Read/Write command cycling Auto Refresh Current Auto refresh command cycling Self Refresh Current Self refresh mode (CKE = 0.2V) ICC6 1 1 1 1 (tCK = min.) ICC5 145 135 125 105 3 CKE = VIL (Power Down mode) (tCK = min.) ICC3P ICC4 3 160 3 155 3 145 3 125 3, 4 CKE = VIL (Power Down mode) CKE = VIH ICC2PS ICC3 1 70 1 65 1 55 1 45 mA CKE = VIL (Power Down mode) CKE = VIH ICC2P ICC2S 1 8 1 8 1 8 1 8 3 CKE = VIH ICC2 55 50 45 40 3 1 bank operation ICC1 105 -6 MAX. 100 -7 MAX. 90 -8 MAX. 80 3 UNIT NOTES
PARAMETER Input Leakage Current (0V VIN VCC, all other pins not under test = 0V) Output Leakage Current 7(Output disable, 0V VOUT VCCQ) LVTTL Output H Level Voltage (IOUT = -2 mA) LVTTL Output "L Level Voltage (IOUT = 2 mA)
SYMBOL II(L)
MIN. -5
MAX. 5
UNIT A
NOTES
VO(L)
-5
5
A
VOH
2.4
-
V
VOL
-
0.4
V
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Publication Release Date: December 1999 Revision A1
W986432AH
AC CHARACTERISTICS
(VCC = 3.3V 0.3V, VSS = 0V, Ta = 0 to 70 C) (Notes: 5, 6, 7, 11) PARAMETER MIN. Ref/Active to Ref/Active Command Period Active to precharge Command Period tRC 60 100000 -55 MAX. MIN. 60 42 18 1 18 12 10 6 1000 1000 10 6 2.5 2.5 7 5 tOH tHZ tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC 11 2 2 0 0 0.3 1.5 1 1.5 1 1.5 1 1.5 1 64 12 5.5 10 5.5 2 2 0 0 0.3 2 1 2 1 2 1 2 1 64 14 6 10 6 7 5.5 2.5 2.5 0 0 0.3 2 1 2 1 2 1 2 1 64 16 7 10 7 1000 1000 100000 -6 MAX. MIN. 70 48 20 1 20 14 10 7 10 7 3 3 7 5.5 3 3 0 0 0.3 2 1 2 1 2 1 2 1 64 mS nS 9 8 10 8 8 1000 1000 100000 -7 MAX. MIN. 72 48 20 1 20 16 10 8 10 8 3 3 7 6 1000 1000 10 10 Cycle nS 100000 -8 MAX. nS 9 9 9 9 9 9 UNIT NOTE
tRAS 38.5
Active to Read/Write Command Delay Time tRCD 16.5 Read/Write(a) to Read/Write(b)Command Period Precharge to Active(b) Command Period Active(a) to Active(b) Command Period Write Recovery Time
CL* = 2 CL* = 3
tCCD tRP tRPD tWR
1 18 11 10 5.5
CLK Cycle Time
CL* = 2 CL* = 3
tCK
10 5.5
CLK High Level CLK Low Level Access Time from CLK
CL* = 2 CL* = 3
tCH tCL tAC
2 2
Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in-Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode Register Set Cycle Time
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W986432AH
(2) A.C Latency Characteristics CKE to clock disable (CKE Latency) DQM to output to HI-Z (Read DQM Latency) DQM to output to HI-Z (Write DQM Latency) Write command to input data (W rite Data Latency) CS to Command input ( CS Latency) Precharge to DQ Hi-Z Lead time CL = 2 CL = 3 Precharge to Last Valid data out CL = 2 CL = 3 Bust Stop Command to DQ Hi-Z Lead time CL = 2 CL = 3 Bust Stop Command to Last Valid Data out CL = 2 CL = 3 Read with Auto-precharge Command to Active/Ref Command CL = 2 CL = 3 Write with Auto-precharge Command to Active/Ref Command CL = 2 CL = 3 1 2 0 0 0 2 3 1 2 2 3 1 2 BL + tRP BL + tRP BL + tRP BL + tRP Cycle + nS Cycle
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W986432AH
Notes: 1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up Sequence
(1) Power up must be performed in the following sequence. (2) Power must be applied to VCC and VCCQ (simultaneously) while all input signals are held in the "NOP" state. The CLK signals must be started at the same time. (3) After power-up a pause of at least 200 i seconds is required. It is required that DQM and CKE signals then be held ` high` (VCC levels) to ensure that the DQ output is impedance. (4) All banks must be precharged. (5) The Mode Register Set command must be asserted to initialize the Mode Register. (6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of the device.
6. AC Testing Conditions
PARAMETER Output Reference Level Output Load Input Signal Levels (VIH/VIL) Transition Time (Rise and Fall) of Input Signal Input Reference Level CONDITIONS 1.4V See diagram below 2.4V/0.4V 1 nS 1.4V
1.4 V
50 ohms
output
Z = 50 ohms 30pF
AC TEST LOAD
1. Transition times are measured between VIH and VIL. 2. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 3. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count fractions as whole number) (1) tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.). tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).
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Publication Release Date: December 1999 Revision A1
W986432AH
TIMING WAVEFORMS
Command Input Timing
tCK
tCL
tCH
VIH CLK VIL
tT tCMS tCMH tCMH tT tCMS
CS
tCMS
tCMH
RAS
tCMS
tCMH
CAS
tCMS
tCMH
WE
tAS
tAH
A0-A10 BS0, 1
tCKS
tCKH
tCKS
tCKH
tCKS
tCKH
CKE
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Publication Release Date: December 1999 Revision A1
W986432AH
Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A10 BS0, 1
tAC tLZ tOH
Valid Data-Out
tAC tOH
tHZ
DQ
Read Command
Valid Data-Out
Burst Length
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W986432AH
Control Timing of Input Data
(Word Mask)
CLK
tCMH tCMS tCMH tCMS
DQM0
tCMH tCMS tCMH tCMS
DQM1
tDS tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ0 -DQ7
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ8-DQ15
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ16 -DQ23
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ24-DQ31
*DQM2,3="L" (Clock Mask)
CLK
tCKH tCKS tCKH tCKS
CKE
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ0 -DQ7
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ8 -DQ15
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ16 -DQ23
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
tDS
tDH
Valid Data-in
DQ24 -DQ31
- 17 -
Publication Release Date: December 1999 Revision A1
W986432AH
Control Timing of Output Data
(Output Enable)
CLK
tCMH tCMS tCMH tCMS
DQM0
tCMH tCMS tCMH tCMS
DQM1
tAC tOH tOH
Valid Data-Out
tAC
tHZ tOH
Valid Data-Out
tAC tLZ tOH
Valid Data-Out
tAC
DQ0 -DQ7
tAC tOH
OPEN
tAC tOH
Valid Data-Out
tAC tOH
Valid Data-Out
tHZ tOH
Valid Data-Out
tAC tLZ
DQ8 -DQ15
tAC tOH
OPEN
tAC tOH
Valid Data-Out
tHZ tOH
Valid Data-Out
tAC tLZ
Valid Data-Out
tAC tOH
Valid Data-Out
DQ16 -DQ23
tAC tOH
tAC tOH
Valid Data-Out
tHZ tOH
Valid Data-Out
tAC tOH
Valid Data-Out
tAC tOH
Valid Data-Out
DQ24 -DQ31
*DQM2,3="L" (Clock Mask)
CLK
tCKH tCKS tCKH tCKS
CKE
tAC tOH tOH
Valid Data-Out Valid Data-Out
tAC tOH
tAC tOH
Valid Data-Out
tAC
DQ0 -DQ7
tAC tOH
tAC tOH
Valid Data-Out Valid Data-Out
tAC tOH tOH
Valid Data-Out
tAC
DQ8 -DQ15
tAC tOH
tAC tOH
Valid Data-Out Valid Data-Out
tAC tOH tOH
Valid Data-Out
tAC
DQ16 -DQ23
tAC tOH
tAC tOH
Valid Data-Out Valid Data-Out
tAC tOH tOH
Valid Data-Out
tAC
DQ24 -DQ31
- 18 -
W986432AH
Mode Register Set Cycle
tRSC
CLK
tCMS tCMH
CS
tCMS
tCMH
RAS
tCMS tCMH
CAS
tCMS tCMH
WE
tAS tAH
Register set data
A0-A10 BS0,1
A0 A1 A2 A3 A4 A5 A6 A7 A0 A8 A0 A9 A10 A11 A0 "0" "0" A0 Reserved "0" "0" (Test Mode) Reserved Write Mode A0 CAS Latency Addressing Mode Burst Length
A2 0 0 0 0 1 1 1 1
A0 A0 A1 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A3 A0 A0 0 A0 1
A0 0 1 0 1 0 1 0 1
next command BurstA0 Length Sequential A0 Interleave A0 1 A0 1 A0 A0 2 2 A0 4 A0 4 A0 8 A0 8 Reserved A0 FullA0 Page Addressing Mode A0 Sequential A0 Interleave A0 A0 Reserved
A6 0 0 0 0 1
A0 A5 A0 0 A0 0 A0 1 A0 1 A0 0 A9 A0 A0 0 A0 1
A4 0 1 0 1 0
CAS A0 Latency Reserved A0 Reserved A0 2 A0 3 Reserved Single Write Mode Burst read and Burst write A0 Burst read and single write A0
BS0 "0" BS1 "0" A0
- 19 -
Publication Release Date: December 1999 Revision A1
W986432AH
OPERATING TIMING EXAMPLE
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRC tRC
tRC tRC tRAS tRP tRAS tRP
RAS
tRAS tRP tRAS
CAS
WE BS0 BS1
tRCD tRCD
RBb RAc
tRCD
RBd
tRCD
RAe
A10
RAa
A0-A9 DQM
RAa
CAw
RBb
CBx
RAc
CAy
RBd
CBz
RAe
CKE
tAC tAC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
tAC
cy0 cy1 cy2 cy3
tAC
DQ
tRRD
tRRD
tRRD
tRRD
Bank #0 Active Bank #1 Bank #2 Idle Bank #3
Read Active
Precharge Read
Active
Read Precharge Active
Precharge Read
Active
- 20 -
W986432AH
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRC tRC tRC tRC tRAS tRP tRP tRAS
RAS
tRAS tRAS tRP
CAS
WE BS0 BS1
tRCD tRCD
RBb RAc
tRCD
tRCD
RBd RAe
A10
RAa
A0-A9
RAa
CAw RBb
CBx
RAc
CAy
RBd
CBz
RAe
DQM CKE
tAC tAC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
tAC
cy0 cy1 cy2 cy3
tAC
dz0
DQ
tRRD
tRRD
tRRD
tRRD
Bank #0 Bank #1 Bank #2 Idle Bank #3
Active
Read Active
AP* Read
Active AP*
Read Active
AP* Read
Active
* AP is the internal precharge start timing
- 21 -
Publication Release Date: December 1999 Revision A1
W986432AH
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRC
RAS
tRAS tRP tRP tRAS tRAS
CAS
WE BS0 BS1
tRCD tRCD
RBb RAc
tRCD
A10
RAa
A0-A9
RAa
CAx
RBb
CBy
RAc
CAz
DQM
CKE
tAC tAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6
tAC
by7 CZ0
DQ
tRRD
tRRD
Bank #0 Active Bank #1 Bank #2 Idle Bank #3
Read Precharge Active Read
Precharge
Active
Read Precharge
- 22 -
W986432AH
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8
t RC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK CS
RAS
tRAS tRP tRAS
CAS
WE BS0 BS1
tRCD tRCD tRCD
RBb RAc
A10
RAa
A0-A9
RAa
CAx
RBb
CBy
RAc
CAz
DQM
CKE
tCAC
tCAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5
tCAC
by6 CZ0
DQ
tRRD
tRRD
Bank #0 Bank #1 Bank #2
Active
Read Active
AP* Read
Active
Read AP*
Idle Bank #3 * AP is the internal precharge start timing
- 23 -
Publication Release Date: December 1999 Revision A1
W986432AH
Interleaved Bank Write (Burst Length = 8)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRC
RAS
tRAS tRP tRAS
CAS
tRCD tRCD tRCD
WE
BS0 BS1
A10
RAa
RBb
RAc
A0-A9
RAa
CAx
RBb
CBy
RAc
CAz
DQM
CKE DQ
ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2
tRRD
tRRD
Bank #0 Bank #1 Bank #2 Bank #3
Active
Write Active Write
Precharge
Active
Write Precharge
Idle
- 24 -
W986432AH
Interleaved Bank Write (Burst Length = 8, Autoprecharge)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRC
RAS
tRAS tRP tRAS
CAS
WE
BS0 BS1
tRCD tRCD
RBb RAb
tRCD
A10
RAa
A0-A9
RAa
CAx
RBb
CBy
RAc
CAz
DQM CKE DQ
ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2
tRRD
tRRD
Bank #0 Active Bank #1 Bank #2 Idle Bank #3
Write Active
AP* Write
Active
Write AP*
* AP is the internal precharge start timing
- 25 -
Publication Release Date: December 1999 Revision A1
W986432AH
Page Mode Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
tCCD tCCD tCCD
CS
tRAS tRAS
RAS
CAS
WE BS0 BS1
tRCD tRCD
RBb
A10 A0-A9 DQM CKE
RAa
RAa
CAI
RBb
CBx
CAy
CAm
CBz
tAC
tAC
a0 a1 a3 bx0
tAC
tAC
tAC
am0 am1 am2 bz0 bz1 bz2 bz3
DQ
tRRD
a2
bx1
Ay0
Ay1
Ay2
Bank #0 Active Bank #1 Bank #2 Idle Bank #3
Read Active Read
Read
Read Read
Precharge AP*
* AP is the internal precharge start timing
- 26 -
W986432AH
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK CS
tRAS
RAS CAS
WE
BS0 BS1
tRCD
A10
RAa
A0-A9
RAa
CAx
CAy
DQM CKE
tAC tWR
ax0 ax1 ax2 ax3 ax4 ax5 ay0 ay1 ay2 ay3 ay4
DQ
QQ
Q
Q
Q
Q
D
D
D
D
D
Bank #0 Bank #1 Bank #2 Bank #3
Active
Read
Write
Precharge
Idle
- 27 -
Publication Release Date: December 1999 Revision A1
W986432AH
Autoprecharge Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRC
RAS
tRAS tRP tRAS
CAS
WE BS0
BS1
tRCD tRCD
RAb
A10
RAa
A0-A9
RAa
CAw
RAb
CAx
DQM CKE
tAC tAC
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
DQ
Bank #0 Bank #1 Bank #2
Active
Read
AP*
Active
Read
AP*
Idle Bank #3 * AP is the internal precharge start timing
- 28 -
W986432AH
Autoprecharge Write (Burst Length = 4)
(CLK = 100 MHz) CLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
tRC tRC
RAS
tRAS tRP tRAS tRP
CAS
WE BS0 BS1
tRCD tRCD
RAb RAc
A10 A0-A9 DQM CKE DQ
RAa
RAa
CAw
RAb
CAx
RAc
aw0
aw1
aw2
aw3
bx0
bx1
bx2
bx3
Bank #0 Bank #1 Bank #2
Active
Write
AP*
Active
Write
AP*
Active
Idle Bank #3 * AP is the internal precharge start timing
- 29 -
Publication Release Date: December 1999 Revision A1
W986432AH
Autorefresh Cycle
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
tRP tRC tRC
CS
RAS
CAS
WE
BS0,1
A10
A0-A9
DQM
CKE DQ
All Banks Prechage
Auto Refresh
Auto Refresh (Arbitrary Cycle)
- 30 -
W986432AH
Self-refresh Cycle
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRP
RAS
CAS
WE
BS0,1
A10
A0-A9
DQM
tSB
tCKS
tCKS
CKE
tCKS
DQ
tRC
Self Refresh Cycle
No Operation Cycle
All Banks Precharge
Self Refresh Entry
Arbitrary Cycle
- 31 -
Publication Release Date: December 1999 Revision A1
W986432AH
Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS RAS
CAS
tRCD
WE BS0
BS1
A10
RBa
A0-A9
RBa
CBv
CBw
CBx
CBy
CBz
DQM CKE
tAC tAC
av0 Q Q av1 Q av2 Q av3 D aw0 D ax0 D ay0 Q az0 Q az1 Q az2 Q az3
DQ
Bank Bank Bank Bank
#0 #1 #2 #3
Active
Read
Single Write
Read
Idle
- 32 -
W986432AH
Power-down Mode
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
WE
BS
A10
RAa
RAa
A0-A9
RAa
CAa
RAa
CAx
DQM
tSB tSB
CKE
tCKS tCKS
ax0 ax1 ax2
tCKS
ax3
tCKS
DQ
Active
NOP
Read
Precharge
NOPActive Precharge Standby Power Down mode
Active Standby Power Down mode
Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode. When CKE goes high, command input must be No operation at next CLK rising edge.
- 33 -
Publication Release Date: December 1999 Revision A1
W986432AH
Auto-precharge Timing (Write Cycle)
0
(1) CAS Latency=2
( a ) burst length = 1 Command
1
2
3
4
5
6
7
8
9
10
11
Write
tWR
AP
tRP
Act
DQ ( b ) burst length = 2 Command
D0 Write
tWR
AP
tRP
Act
DQ ( c ) burst length = 4 Command
D0 Write
D1 AP
tWR tRP
Act
DQ ( d ) burst length = 8 Command
D0 Write
D1
D2
D3 AP
tWR tRP
Act
DQ
D0 Write
tWR
D1 AP
(2) CAS Latency=3
( a ) burst length = 1 Command
D2
D3
D4 Act
D5
D6
D7
tRP
DQ ( b ) burst length = 2 Command
D0 Write
tWR
AP
tRP
Act
DQ ( c ) burst length = 4 Command
D0 Write
D1 AP
tWR tRP
Act
DQ ( d ) burst length = 8 Command
D0 Write
D1
D2
D3 AP
tWR tRP
Act
DQ
D0
D1
D2
D3
D4
D5
D6
D7
Note:
Write AP Act represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min.)
- 34 -
W986432AH
Auto-precharge Timing (Read Cycle)
0
(1) CAS Latency=2
( a ) burst length = 1 Command
1
AP
2
3
Act
4
5
6
7
8
9
10
11
Read
tRP
DQ ( b ) burst length = 2 Command DQ ( c ) burst length = 4 Command DQ ( d ) burst length = 8 Command
Q0 Read AP
tRP
Act Q1 AP
tRP
Q0 Read Q0 Read Q0
Act Q3 AP
tRP
Q1
Q2
Act
DQ
Q1
Q2
Q3
Q4
Q5
Q6
Q7
(2) CAS Latency=3
( a ) burst length = 1 Command
Read
AP
tRP
Act Q0
DQ ( b ) burst length = 2 Command DQ ( c ) burst length = 4 Command DQ ( d ) burst length = 8 Command
Read
AP
tRP
Act Q0 Q1 AP
tRP
Read Q0 Read Q0
Act Q2 Q3 AP
tRP
Q1
Act Q6 Q7
DQ
Q1
Q2
Q3
Q4
Q5
Note: Read AP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least RAS (min). t
- 35 -
Publication Release Date: December 1999 Revision A1
W986432AH
Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
0
(1) CAS Latency=2
( a ) Command
1
Read
2
Write
3
4
5
6
7
8
9
10
11
DQM
DQ
D0 Read
D1 Write
D2
D3
( b ) Command
DQM
DQ
D0 Read Write D0 Read D1 Write
D1
D2
D3
(2) CAS Latency=3
( a ) Command DQM
DQ ( b ) Command DQM
D2
D3
DQ
D0
D1
D2
D3
Note: The Output data must be masked by DQM to avoid I/O conflict.
- 36 -
W986432AH
Timing Chart of Write to Read Cycle
In the case of Burst Length = 4
0
(1) CAS Latency = 2
( a ) Command DQM DQ
1
Write D0 Write D0
2
Read
3
4
5
6
7
8
9
10
11
Q0 Read D1
Q1
Q2
Q3
( b ) Command DQM DQ
Q0
Q1
Q2
Q3
(2) CAS Latency = 3
( a ) Command DQM DQ ( b ) Command DQM
Write D0 Write D0
Read Q0 Read D1 Q0 Q1 Q2 Q3 Q1 Q2 Q3
DQ
- 37 -
Publication Release Date: December 1999 Revision A1
W986432AH
Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
(3) Read cycle
( a ) CAS latency =2
Command
1
2
3
4
5
6
7
8
9
10
11
Read Q0 Read Q0 Write D0 D1 D2 D3 D4 Q1 Q1 Q2
BST Q3 BST Q2 BST Q3 Q4 Q4
DQ
( b ) CAS latency = 3
Command
DQ
(2) Write cycle
Command
DQ
Note:
BST
represents the Burst stop command
- 38 -
W986432AH
Timing Chart of Burst Stop Cycle (Precharge Command)
In the case of Burst Lenght = 8
0
(1) Read cycle ( a )CAS latency =2
Commad
1
2
3
4
5
6
7
8
9
10
11
Read Q0 Read Q0 Q1 Q1 Q2
PRCG Q3 PRCG Q2 Q3 Q4 Q4
DQ
( b )CAS latency = 3
Commad
DQ
(2) Write cycle ( a ) CAS latency =2
Commad DQM DQ
Write
PRCG
tWR
D0 Write
D1
D2
D3
D4
PRCG
tWR
( b ) CAS latency = 3
Commad
DQM DQ
D0
D1
D2
D3
D4
Note:
PRCG
represents the Precharge command
- 39 -
Publication Release Date: December 1999 Revision A1
W986432AH
CKE/DQM Input Timing (Write Cycle)
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
D1
D2
D3
DQM MASK (1)
D5
CKE MASK
D6
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
D1
D2
D3
DQM MASK (2)
D5
CKE MASK
D6
CLK cycle No. External CLK Internal CKE DQM DQ
1
2
3
4
5
6
7
D1
D2
D3
CKE MASK (3)
D4
D5
D6
- 40 -
W986432AH
CKE/DQM Input Timing (Read Cycle)
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM
DQ
Q1
Q2
Q3
Q4
Open Open
Q6
(1)
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
Q1
Q2
Q3
Q4
Open
Q6
(2)
CLK cycle No.
1
2
3
4
5
6
7
External CLK Internal CKE DQM DQ
Q1
Q2
Q3
Q4
Q5
Q6
(3)
- 41 -
Publication Release Date: December 1999 Revision A1
W986432AH
Self Refresh/Power Down Mode Exit Timing
Asynchronous Control Input Buffer turn on time (Power down mode exit time) is specified by t A ) tCK < tCKS (min.) + tCK (min.)
tCK
CKS (min.)
+ tCK (min.)
CLK CKE
tCKS(min) +tCK(min)
Command
NOP
Command
Input Buffer Enable
B) tCK >= tCKS (min.) + tCK (min.)
tCK CLK
CKE
tCKS(min) +tCK(min)
Command
Command
Input Buffer Enable
Note: All Input Buffer (Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode
NOP Command
Represents the No-Operation command Represents one command
- 42 -
W986432AH
PACKAGE DIMENSIONS
86L TSOP (II)-400 mil
86
44
E
HE
1 e D b
43
C
q L A2 ZD A1 A L1
Y
SEATING PLANE
Controlling Dimension: Millimeters
DIMENSION (MM)
SYM.
DIMENSION (INCH) MAX.
1.20 0.15
MIN. A
A1 A2 b c D E HE e L L1 Y ZD 0.05
NOM.
MIN.
0.002
NOM.
MAX.
0.047 0.006
1.00 0.17 0.12 22.12 10.06 11.56 0.40 22.22 10.16 11.76 0.50 0.50 0.80 0.10 0.61 0.60 0.016 0.27 0.21 22.62 10.26 11.96 0.007 0.005 0.871 0.396 0.455
0.039 0.011 0.008 0.875 0.400 0.463 0.020 0.020 0.032 0.004 0.024 0.024 0.905 0.404 0.471
- 43 -
Publication Release Date: December 1999 Revision A1
W986432AH
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 44 -

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